In an I/O (input-output) system with a forwarded clock architecture, there is a need for an apparatus at the receive side to measure and adjust the placement of a clock edge in time very precisely relative to other edges under any environmental conditions that a computer system would normally be exposed to. Due to very strict requirements in-particular for high-frequency operation for such an apparatus, the placement of the clock must be very precise relative to an ideal location. The finer the control the apparatus has over the placement of the clock, the higher the data transfer rates that can be achieved. In addition to very fine steps, the apparatus must also be able to have a very wide range of control to account for manufacturing tolerances, device performance, and environmental conditions. Environmental conditions also change while data is being transferred. So, the apparatus should be able to continuously update the clock placement while not interfering with data transfers.
Analog delay locked loops (DLLs) or other analog based clock placement schemes have historically performed the clock placement task by locking on to the cycle time of an incoming clock and providing various choices for clock placement. However, analog DLLs typically consume higher power and may not be suitable for low power applications. Analog DLLs also often suffer from slow start and re-start issues. Delay lines in DLLs also commonly suffer from non-monotonic delay steps that may cause the clock edge to be misaligned relative to data resulting in incorrect sampling of data by the clock edge.